On-chip method and apparatus for transmission of multiple bits using quantized voltage levels

ABSTRACT

A method and apparatus are disclosed for transmitting multiple bits among nodes on a chip using quantized voltage levels. Multiple level logic bus drivers and receivers communicate over a bus using a multiple-level logic protocol that transfers multiple bits on each signal wire of a bus in a given interval without increasing the bus width or power dissipation. In an exemplary embodiment, four logic levels are employed using CMOS transistor circuitry operating with low voltage (e.g., 1.2V or 1.3V) power supplies (V dd ) and P and N transistor threshold voltage levels of V tp  and V tn  on the order of 0.4−0.5V. Thus, the separation between the following four logic levels is approximately uniform: V dd ; V dd −V tp ; V ss +V tn ; and V ss . The approximately equal voltage gaps between each quantization level provide uniform noise margins for all levels. In addition, since the absolute magnitude of the coupling noise is much lower, it requires less active power to recover from an AC injected noise source. The number of physical wires on the bus is reduced by at least half for the same number of bits. The total transition power is reduced by more than fifty percent (50%) since some of the signal transitions are less than rail-to-rail. A bus noise minimization scheme and a quick recovery scheme are also disclosed to ensure the correct data transfer in the presence of injected noise. An initial over drive feature is disclosed for shorter transition times.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present invention is related to U.S. patent applicationentitled “Method and Apparatus for Distributing a Self-SynchronizedClock to Nodes on a Chip,” (Attorney Docket Number Lee 14-5-3), U.S.patent application entitled “Method and Apparatus for TransferringMulti-Source/Multi-Sink Control Signals Using a Differential SignalingTechnique,” (Attorney Docket Number Fernando 9-11-4), U.S. patentapplication entitled “Method and Apparatus for DistributingMulti-Source/Multi-Sink Control Signals Among Nodes on a Chip,”(Attorney Docket Number Fernando 10-12-5) and U.S. patent applicationentitled “Bidirectional Bus Repeater for Communications on a Chip,”(Attorney Docket Number Hunter 4-13-4), each filed contemporaneouslyherewith, assigned to the assignee of the present invention andincorporated by reference herein.

FIELD OF THE INVENTION

[0002] The present invention relates generally to communications on asingle chip, and more particularly, to a technique for transmittingmultiple-level signals on each wire of the single chip.

BACKGROUND OF THE INVENTION

[0003] Address and data busses provide data paths that are shared by anumber of data processing devices, such as memory devices,micro-controllers, microprocessors, digital signal processors (DSPs) andperipheral devices. Busses are typically formed on printed circuitboards (PCBs) and interconnect the various devices mounted on the PCB.The busses may also extend to connectors in order to allow externaldevices to be coupled to the bus.

[0004] Recently, integrated circuit (IC) manufacturers have begunproducing single chips containing multiple device cores, such asmultiple memory devices, micro-controllers, microprocessors and digitalsignal processors (DSPs), that were traditionally mounted on a PCB andinterconnected by one or more busses on the PCB. Such a single chip iscommonly referred to as a system-on-a-chip (SoC). SoCs incorporate oneor more busses to provide data paths to interconnect the multiple coredevices on the chip, often referred to as “nodes.” The busses on SoCs,however, comprise conductor traces on the chip and thus tend to be muchshorter in length than PCB busses.

[0005] As SoCs grow in size and complexity, the requirement ofcommunicating control and data signals between various nodes or deviceson the SoC becomes more difficult, primarily due to theresistive-capacitive (RC) delays attributed to the conductor length. Tomeet customer expectations for increasing performance, DSP andmicroprocessor architects are adopting wider buses for address and datasignals used to communicate with memory and peripheral devices.Consequently, the area and power required for these buses to operate canbecome a very significant portion of the total device size (cost) andpower budget.

[0006] A need therefore exists for a method and apparatus fortransmitting additional data on a chip without increasing the bus widthor power dissipation. A number of techniques have been proposed orsuggested in the data transmission domain for improving transmissionperformance. Computer modem devices operating in the 1200 to 9600bits-per-second (baud) range, for example, convert short strings ofdigital bits into phase or amplitude modulated sinusoidal carriersignals (or both). Thus, multiple bits may be converted to quadraturephaseshift modulation of various frequency sinusoids and the carriersignal may be transmitted long distances without losing its informationcontent. While this technique performs well for long distancetransmissions, it is not well suited to on-chip environment of thepresent invention. Specifically, the length of the wire trace is shorterthan the required wavelength and the signal cannot modulate. 10BASE-TEthernet systems use a bit-serial transmission scheme over twisted pairsto transmit data over distances on the order of 100 meters. The data isrepresented by current transitions that are coupled on-to and off-of theline through transformers. Within one bit interval, the data value isrepresented as either one transition or two transitions. For example, ahigh-to-low transition might represent the value zero (0), while alow-to-high-to-low transition pair might represent the value one (1).The guaranteed presence of transitions makes clock recovery possible andhence provides reliable data recovery. While this technique performswell for transmissions of reasonably long length, it is not well-suitedto on-chip environment of the present invention. Specifically, theinductive coupling of signals onto the transmission line associated withthe 10BASE-T Ethernet standard would be difficult to achieve in normalCMOS processing.

[0007] Discrete voltage levels have been used to store information. Oneexample of a multi-level storage system is a 2 bits-per-cell dynamicrandom access memory (DRAM) from Toshiba, as described in Betty Prince,“Semiconductor Memories,” 334 (1989). Each cell stores one of fourvoltage (charge) levels to record two bits of information. The output ofthe cell is compared in parallel with three reference levels positionedat the mid-range points to determine the stored value. A second exampleof a multi-level charge storage system is the StrataFlash non-volatilememory technology from Intel Corp. The StrataFlash memory also stores 2bits-per-cell using four voltage (charge) levels.

[0008] These existing multi-level memory devices demonstrate that CMOScircuits can be built to reliably detect at least four voltage levels.Both memories use reference voltages and sense amplifiers todiscriminate voltage levels that are proportional to the stored charge.In a memory, each sense amplifier is shared by many storage cells, andthe number of outputs is relatively small, on the order of 1 or 4outputs for a DRAM and 8 or 16 outputs for a Flash electronicallyerasable programmable read only memory (EEPROM). For a SoC busapplication, however, the bus may be 128 or more bits wide, and eachreceiving module would need a set of sense amplifiers. Hence, linearsense amplifiers may not be practical for a bus application because ofthe high active power dissipation.

SUMMARY OF THE INVENTION

[0009] Generally, a method and apparatus are disclosed for transmittingmultiple bits among nodes on a chip using quantized voltage levels. Eachnode on the chip includes a multiple level logic bus driver and receiverfor communicating over a bus using a multiple-level logic protocol inaccordance with the present invention. The multiple-level logic protocoltransfers multiple bits on each signal wire of the bus in a given timeinterval without increasing the bus width or power dissipation.

[0010] In an exemplary embodiment, four logic levels are employed usingCMOS transistor circuitry operating with low voltage (e.g., 1.2V or1.3V) power supplies (V_(dd)) and P and N transistor threshold voltagelevels of V_(tp) and V_(tn) on the order of 0.4-0.5V. Thus, theseparation between each voltage level is approximately uniform. Theexemplary quad logic level quantization divides the supply voltage levelinto approximately 3 equal parts such that the gap between each logiclevel becomes 0.4V to 0.5V in the exemplary embodiment. Thus, four logicSecond, since the absolute magnitude of the coupling noise is muchlower, it requires less active power to recover from an AC injectednoise source. In addition, the number of physical wires on the bus canbe reduced by at least half for the same number of bits transferred. Thepresent invention also reduces the total transmission power by more thanfifty percent (50%) since some of the signal transitions are less thanrail-to-rail.

[0011] A bus noise minimization scheme and a quick recovery scheme arealso disclosed to ensure the correct data transfer in the presence ofinjected noise. The disclosed quad logic level bus driver includes ahigh impedance equalizer transistor that serves as a noise minimizer andallows quick recovery from an injected noise transient. Another aspectof the invention, provides an initial over drive for shorter transitiontimes. One characteristic of transistor circuits employing low powersupply voltages (i.e., V_(dd) approximately equal to 3V_(t)) is that thevoltage level of logic α and β states are very close to the N and Ptransistor threshold voltage levels (V_(tn) and V_(dd)−V_(tp),respectively). Thus, when logic α is driven on a bus wire, the receiverwould not be able to quickly distinguish the α logic level from logic‘0’ (V_(ss)). Therefore, to overcome this problem and to ensure quickdata transfer, the circuit portion of this invention includes a dataover driver circuit within the bus driver such that, when the data onthe bus changes from 1 or 0 to either α or β, the over drive circuitbecomes active and drives the bus wire with V_(ss)+V_(tn) (orV_(dd)−V_(tp)).

[0012] A more complete understanding of the present invention, as wellas further features and advantages of the present invention, will beobtained by reference to the following detailed description anddrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a schematic block diagram illustrating a conventionalSoC where the present invention can operate,

[0014]FIG. 2 illustrates a multiple level logic bus driver and receivercommunicating over a common bus in accordance with the presentinvention;

[0015]FIG. 3 is a table illustrating the assignment of various voltagelevels to corresponding binary values in a quad logic level embodimentof the present invention;

[0016]FIG. 4 is a circuit diagram illustrating an exemplary digitalcircuit implementation of a logic level β generator in accordance withthe present invention;

[0017]FIG. 5 is a circuit diagram illustrating an exemplary digitalcircuit implementation of a logic level α generator in accordance withthe present invention;

[0018]FIG. 6 is a circuit diagram illustrating an exemplary digitalcircuit implementation of a quad logic level bus driver (QLLBD) inaccordance with the present invention;

[0019]FIG. 7 is a circuit diagram illustrating an exemplary digitalcircuit implementation of a quad logic level detector (QLLD) used in aquad logic level bus receiver (QLLBR) in accordance with the presentinvention; and

[0020]FIG. 8 is a circuit diagram illustrating an exemplary digitalcircuit implementation of a quad logic level decoder used in a quadlogic level bus receiver (QLLBR) in accordance with the presentinvention.

DETAILED DESCRIPTION

[0021]FIG. 1 is a schematic block diagram illustrating an exemplary SoC100 where the present invention can operate. The exemplary SoC 100includes a bus 110 that interconnects various nodes 120-1 through 120-N(multiple core devices), collectively referred to as nodes 120, on thechip 100. The nodes 120 may be embodied, for example, as memory devices,microcontrollers, microprocessors and digital signal processors (DSPs).When an SoC 100 includes multiple nodes 120 communicating over a commonbus 110, an Arbiter 150 is often used to determine which node 120 shouldactively drive the bus 110 at a particular time. Multi-source/multi-sinkcontrol signals, such as acknowledgement (ACK), data-valid, interruptand error signals, are often employed to control communications on theSoC bus 110. All of the various nodes 120 and the Arbiter 150 typicallyoperate synchronously with respect to a common clock 160.

[0022]FIG. 2 illustrates a multiple level logic bus driver 210associated with a first node A and a multiple level logic bus receiver220 associated with a node B communicating over the common bus 110 ofFIG. 1 in accordance with the present invention. The logic bus driver210 and logic bus receiver 220 employ a multiple-level logic protocol totransfer multiple bits on each signal wire of the bus 215 in a giveninterval without increasing the bus width or power dissipation. Whilethe present invention is illustrated herein in an exemplary SoCenvironment, the present invention is applicable to any environmentwhere bits are transmitted from one device to another over a common busline. Exemplary quad logic implementations of the logic bus driver 210are discussed further below in conjunction with FIGS. 4 through 6 andexemplary quad logic implementations of the logic bus receiver 220 arediscussed further below in conjunction with FIGS. 7 and 8.

[0023] In the exemplary embodiment of the present invention, four logiclevels are employed using CMOS transistor circuitry operating with 1.2Vor 1.3V power supplies (V_(dd)) and P and N transistor threshold voltagelevels of V_(tp) and V_(tn) on the order of 0.4-0.5V. Among otherbenefits, such CMOS transistors are selected due to the uniformity ofthe voltage level separation. The exemplary quad logic levelquantization divides the supply voltage level into approximately 3 equalparts such that the gap between each logic level becomes 0.4V to 0.5V.As shown in FIG. 3, each logic level is then approximately defined asfollows: V_(dd) (1.2V−1.3V); V_(dd)−V_(tp) (0.8V); V_(ss)+V_(tn) (0.4V);and V_(ss) (0V). An exemplary binary, symbolic and decimal bitallocation for each level is shown in fields 322-324 of FIG. 3. Ofcourse, variations on the precise voltage levels and correspondingbinary assignments shown in FIG. 3 are possible, as would be apparent toa person of ordinary skill in the art.

[0024] The lower supply voltage employed by the present inventionprovides two inherent advantages, compared to a higher power supply(over 2V). First, as indicated above, since the voltage gaps betweeneach quantization level are approximately equal, the noise margins forall levels are the same. Thus, it is easier to design the noiserecovery/immunity circuit and the circuitry is not biased towards anyparticular level. Second, since the absolute magnitude of the couplingnoise is much lower, it requires less active power to recover from an ACinjected noise source.

[0025] As previously indicated, four logic levels on a bus wire permitstwo bits of data to be transmitted on a single wire in each interval.Therefore, the number of physical wires on the bus 215 can be reduced inhalf for the same number of bits. It has also been observed that thereduction in total transition power is more than fifty percent (50%)because some of the signal transitions are less than rail-to-rail.

[0026] The voltage gap between any two logic levels is one third of thevoltage gap of the two logic levels of bi-level logic. Thus, to ensurethe correct data transfer, it is important to implement a bus noiseminimization scheme and a quick recovery scheme from any injected noise.According to one feature of the invention discussed below in conjunctionwith FIGS. 4-6, the circuit implementation of the quad logic level busdriver includes a high impedance equalizer transistor that serves as anoise minimizer and allows quick recovery from an injected noisetransient. The disclosed noise recovery mechanism circuit toleratesrail-to-rail noise (1.2V in the exemplary embodiment).

[0027] Another feature of the present invention, discussed furtherbelow, provides an initial over drive for a shorter transition time. Onecharacteristic of transistor circuits employing low power supply voltage(V_(dd) approximately equal to 3V_(t)) is that the voltage level oflogic α and β states are very close to the N and P transistor thresholdvoltage levels (V_(tn) and V_(dd)−V_(tp), respectively). Thus, whenlogic α is driven on a bus wire, the receiver would not be able toquickly distinguish the α logic level from logic ‘0’ (V_(ss)).Therefore, to overcome this problem and to ensure quick data transfer,the circuit portion of this invention includes a data over drivercircuit within the bus driver such that, when the data on the buschanges from 1 or 0 to either α or β, the over drive circuit becomesactive and drives the bus wire with V_(ss)+V_(tn) (or V_(dd)−V_(tp)).

Quad Logic Level Bus Driver (QLLBD)

[0028] FIG. through 6 illustrate a way of realizing the Quad Logic LevelBus Driver (QLLBD) with COM2 digital circuits. The normalized transistorsizes are given with the type of transistors in each figure for anexemplary implementation. FIG. 4 is a circuit diagram illustrating anexemplary digital circuit implementation of α logic level β generator400. The control signal, CNTL, shown in FIG. 4 only becomes active(V_(SS)) when a node 120 needs to drive the SoC bus 110 (FIG. 1). WhenCNTL is inactive, the PMOS transistors, MP2 and MP4, are shut off andthe output nodes, β and 2V_(TP), are pulled down to V_(SS). Thus, iteliminates any DC power consumption. Likewise, when CNTL is active, theoutput node β is driven to V_(DD)−V_(tp), and the node 2V_(TP) is drivento V_(DD)−2V_(tp), where V_(tp) is the specied PMOS threshold voltage.The bus line driver consists of transistors MP1, MP2 and MN1, and thetransistors, MP3-MP5 and MN4-MN5, serve as the bus noise recoverytransistors. The transistors MP4A and MP5 are configured as very weakdiodes that are used to discharge any charge built up due to noiseinjection on these nodes. The output node 2V_(TP) is used to recover thebus signal from any cross talk noise injected on the bus wire. Adetailed description of the bus noise recovery mechanism is given in asection entitled “Noise Recovery Mechanism.”

[0029]FIG. 5 is a circuit diagram illustrating an exemplary digitalcircuit implementation of a logic level α generator 500. The operationof this circuit is almost identical to the operation of the logic levelβ generator 400, discussed above. In this case, the active level of thecontrol signal, CNTL, is V_(DD). Thus, unless the node 120 needs todrive the bus 110, CNTL is driven with V_(SS), and the NMOS transistors(MN1 and MN3) are shut off to eliminate any DC power consumption. Again,just as for the logic level β generator 400, the transistors, MP3-MP5and MN4-MN5A, serve as the bus noise recovery transistors.

[0030]FIG. 6 is a circuit diagram illustrating an exemplary digitalcircuit implementation of the quad logic level bus driver (QLLBD) 600.The transistors MPT1, MPT, MNT and MNT0 are configured as a multiplexerwith inputs tied to four logic levels. The active level of the controlsignals DRV_1 and DRV_β is low (V_(SS)), and the active level of DRV_αand DRV_0 is high (V_(DD)). The output of this driver (QD_SIG)represents the encoded value of a two bit binary number such that binary00 is represented by the logic level 0, 01 is represented by α, 10 by βand binary 11 by the logic level 1.

Bus Over-Drive

[0031] An important criteria for designing a multiple logic level bus isthat each logic level is well distinguished by any receiver 220connected to the bus 110. This criteria is not easy to satisfy when theoperating voltage is equal to 3V_(t). As previously indicated, when thepower supply voltage is 3V_(t), the quad logic levels are quantizednicely into four levels with equal separation amongst them. However, thevoltage level of each logic state is not well recognized by thereceiver. For example, the voltage level of logic level α is V_(tn), theNMOS threshold voltage. This voltage level can turn on the NMOStransistors in the receivers 220, but the ‘ON’ state is weak and itwould produce a very slow signal transition on the outputs of thereceiver. Thus, the data transfer rate suffers and the power dissipationincreases.

[0032] Thus, the present invention incorporates a bus over-drivingmechanism in the logic level generators 400, 500 and QLLBD 600 toenhance the data transfer rate and to minimize the transient (switch)power. An operational example of the bus over-driving mechanism isdiscussed herein for the case when a bus wire is driven with β.Referring to FIGS. 4 through 6,there are three time intervals (T₀−,T₀+and T₀++) relevant to the over-driving mechanism:

[0033] T₀−. The bus 110 is not yet driven by the node 120-i—CNTL andDRV_β are inactive (V_(DD)), node β is low (V_(SS)), node 2V_(TP) is low(V_(SS)). Thus, the transistors MPT and MPFB are off, and the transistorMPFA is on.

[0034] T₀+. The node 120-i just starts to drive the bus 110—CNTL andDRV_β become active (V_(SS)), but node β and node 2V_(TP) are still low(V_(SS)), the transistors MPT and MPFB turn on first before thetransistor MPFA shut off.

[0035] Thus, a direct DC path is created to ground from the bus wire(QD_SIG) via MPFB-MPFA (FIG. 6), and discharges the bus wire whichcauses a down swing of the bus voltage level to a value below the logiclevel β. The amount of down swing is controlled by properly sizing thetransistors, and the bus is over driven by the voltage differencebetween the down swing level and the logic β level. The exemplaryover-drive is approximately 0.15V for the α driver and 0.1 8V for the βdriver.

[0036] T₀++. The module drives the bus wire with the logic level β —MPFAshuts off and the bus wire (QD-SIG) in FIG. 6 is driven to the logiclevel β by transistors MP1 and MP2 (FIG. 4).

[0037] The operation of the bus over driving mechanism for driving thebus 110 with the logic level α is very similar to the case described atabove for the β level.

Noise Recovery Mechanism

[0038] Consider the case when the signal level on the wire QD_SIG is β.In this case, if a noise injection into the wire causes the wire voltageto swing downward, the driver transistor MP1, MP2 (FIG. 4) and MPT (FIG.6) can pull up the voltage on the wire back to the logic level β.However, if the injected noise causes the voltage to move upward, thelogic level on the wire can not be recovered unless there is a mechanismto discharge the injected charge due to noise. For this purpose, a noiserecovery mechanism is implemented in the Logic Level β generator 400 andthe bus driver 600. The noise recovery mechanism consists of a group oftransistors to produce a stable noise recovery reference voltage(2V_(TP)) for the QLLBD 600 (FIG. 6). The node 2V_(TP) (FIG. 4) isconnected to the transistor MPFA (FIG. 6) such that whenever crosstalknoise couples into QD_SIG and raises the QD_SIG voltage level above β,MPFA turns on to discharge the wire back to the logic β level.

[0039] The operation of the noise recovery mechanism while driving α (onQD_SIG) is very similar with the case described above for the β level.In the α case, whenever the voltage on QD_SIG swings downward below thevoltage level of α NNFA turns on and charges the wire QD_SIG back to thelogic level α. It has been observed that when the injected noise causesthe two bus wires to swing all the way to V_(DD) and V_(SS), the noiserecovery circuit of the present invention ensures that the bus wiresquickly recover from the effect of any cross coupled noise.

Quad Logic Level Bus Receiver (QLLBR)

[0040] The quad logic level bus receiver (QLLBR) consists of a quadlogic level detector (QLLD) 700, discussed below in conjunction withFIG. 7, and a decoder 800, discussed below in conjunction with FIG. 8.As shown in FIG. 7, the QLLD 700 contains six inverters 710-712 and720-722, with three input inverters 720-722 operating to detect thelogic levels on the bus wire QD_SIG, and three inverters 710-712operating to refine the waveform. The function of THE QLLD 700 is toconvert the quad logic level input to binary indication signals suchthat each detect signal (det_α, β and 01) indicates the presence of acertain logic level at the bus wire QD_SIG. In FIG. 7, the transistorsizes are selected such that each input inverter switch point favors acertain input logic level over the others. For example, the NMOS to PMOSratio of the input inverter det_α_1 is 20. With this ratio, when theinput level is α, although MP1 and MN1 are both on, the output is drivento V_(SS) because the transconductance of MN1 is much greater than thetransconductance of MP1. In fact, the output of the det_α_1 inverteronly goes (binary) high when the input is (quad logic) 0.

[0041] The decoder 800 is implemented with conventional CMOS logic gatesthat perform the function indicated in FIG. 6. The fully decoded finalsignals (BO and B1) are shown in FIG. 7.

[0042] The present invention reduces the physical size of a SoC bus byat least fifty percent (50%) for the same bandwidth and reduces thepower dissipation by at least sixty percent (60%), since a data/addressbus connected to a quad logic level driver/receiver 210, 220 requiresabout ⅓ of the power that would be needed to drive the bus 110 with aconventional driver (bilogic-levels 1 and 0). In addition, the dataover-drive circuit and the noise recovery circuit features of thepresent invention allow the quad logic level (SoC) bus 110 to beoperative for low voltage conditions, such as 1.3 V. Since the inventioncan be implemented with digital circuitry, it makes it easier totransport the circuit from one technology to another technology. Thepresent invention also provides a standard interface to/from nodes 120,since the input signals to the bus driver 210 and the output signalsfrom the bus receiver 220 are binary (data/address) I/O signals and anyexisting IP block can be connected to the quad logic level bus as is.

[0043] It is to be understood that the embodiments and variations shownand described herein are merely illustrative of the principles of thisinvention and that various modifications may be implemented by thoseskilled in the art without departing from the scope and spirit of theinvention.

We claim:
 1. A method for communicating multiple bits among a pluralityof nodes on a chip, said method comprising the steps of: establishing aplurality of voltage levels on said chip; and communicating over a bususing a multiple-level logic protocol
 2. The method of claim 1, whereinsaid plurality of voltage levels are substantially uniform.
 3. Themethod of claim 1, wherein said plurality of voltage levels are achievedusing power supply voltages and threshold voltages of transistors onsaid chip.
 4. The method of claim 3, wherein said transistors are lowvoltage CMOS transistors.
 5. The method of claim 4, wherein said lowvoltage CMOS transistors utilize a power supply voltage of approximately1.2V and have threshold voltages of approximately 0.4V.
 6. The method ofclaim 4, wherein said power supply voltages and threshold voltagesprovide a uniform level separation of approximately 0.3V.
 7. The methodof claim 3, wherein said power supply voltages and threshold voltagesestablish four logic levels as follows: V_(dd); V_(dd)−V_(tp);V_(ss)+V_(tn); and V_(ss), where V_(dd) is the power supply voltage,V_(ss) is 0V, V_(tp) is the P-transistor threshold voltage level andV_(tn) is the N-transistor threshold voltage level.
 8. A chip having aplurality of nodes, said chip comprising: a common bus forcommunications between said nodes; a first node having a multiple levellogic bus driver that transmits multiple bits on a wire of said bus in agiven time interval; and a second node having a multiple level logic busreceiver that receives said multiple bits on said bus.
 9. The chip ofclaim 8, wherein said multiple levels are substantially uniform.
 10. Thechip of claim 8, wherein said multiple levels are achieved in saidmultiple level logic bus driver using power supply voltages andthreshold voltages of transistors on said chip.
 11. The chip of claim10, wherein said transistors are low voltage CMOS transistors.
 12. Thechip of claim 11, wherein said low voltage CMOS transistors utilize apower supply voltage of approximately 1.2V and have threshold voltagesof approximately 0.4V.
 13. The chip of claim 10, wherein said powersupply voltages and threshold voltages provide a uniform levelseparation of approximately 0.3V.
 14. The chip of claim 10, wherein saidpower supply voltages and threshold voltages establish four logic levelsas follows: V_(dd); V_(dd)−V_(tp); V_(ss)+V_(tn); and V_(ss), whereV_(dd) is the power supply voltage, V_(ss) is 0V, V_(tp) is theP-transistor threshold voltage level and V_(tn) is the N-transistorthreshold voltage level.
 15. A method for communicating multiple bitsamong a plurality of nodes on a chip, said method comprising the stepsof: establishing a plurality of voltage levels on said chip using powersupply voltages and threshold voltages of transistors on said chip; andcommunicating over a bus using a multiple-level logic protocol
 16. Themethod of claim 15, wherein said plurality of voltage levels aresubstantially uniform.
 17. The method of claim 15, wherein saidtransistors are low voltage CMOS transistors.
 18. The method of claim17, wherein said low voltage CMOS transistors utilize a power supplyvoltage of approximately 1.2V and have threshold voltages ofapproximately 0.4V.
 19. The method of claim 15, wherein said powersupply voltages and threshold voltages provide a uniform levelseparation of approximately 0.3V.
 20. The method of claim 15, whereinsaid power supply voltages and threshold voltages establish four logiclevels as follows: V_(dd); V_(dd)−V_(tp); V_(ss)+V_(tn); and V_(ss),where V_(dd) is the power supply voltage, V_(ss) is 0V, V_(tp) is theP-transistor threshold voltage level and V_(tn) is the N-transistorthreshold voltage level.